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6月29日 Intel大连将直接用65nm工艺5月19日 英特尔公布上网本操作系统Moblin部分细节(zz)英特尔公布上网本操作系统Moblin部分细节(图)http://www.sina.com.cn 2009年05月20日 03:32 新浪科技
英特尔公布新款Moblin v2界面截图 新浪科技讯 北京时间5月20日凌晨消息，据国外媒体报道，英特尔周二首次公布了用于上网本的新款Atom芯片和Moblin操作系统的部分细节。 代号为Pineview的新款Atom芯片预计将在今年第四季度发布。在这款产品中，英特尔首次将微处理器与两块特征图形电路及一块存储控制器结合在一起，从而组成了一套芯片组。 英特尔上网本及Nettop部门的总经理Noury Al-Khaledy称，这就意味着，生产上网本仅需另外一块主芯片，也就是所谓的“输入输出控制器”，而不是总共三块芯片，其结果就是PC厂商的生产成本以及PC耗电量都将因此降低。 此外，英特尔还披露了新测试版Mobilin操作系统的可用性。英特尔软件及服务集团副总裁道格·费舍尔(Doug Fisher)称，Moblin 2.0版本拥有名为“M-zone(动感地带)”的新界面，旨在简化用户播放数字媒体、使用互联网及社交网络的方式。 英特尔称，操作系统经销商可改编Mobilin操作系统。费舍尔表示，这些经销商将在今年夏天获得它们需要的所有东西，允许其在年底以前发货。(唐风) 2月23日 Intel Inside--Everything最新的一篇Forbes对intel的采访。一些concept还是挺重要的。例如，云计算：Fundamentally，这是存储、计算和通讯三者的平衡。从技术趋势上讲，存储是最容易提高的，计算其次，最难的是通讯。这个里所说的难易，应该是考虑成本的技术改进。 Intel Inside--EverythingEd Sperling, 02.23.09, 03:00 AM ESTChip maker looks for growth opportunities in existing and new markets.Intel's chips have become so pervasive that they are the de facto (concerning the fact，实际上的) standard in computers. Now the company is looking to include them in everything from cars to medical devices to handheld devices. For Intel (nasdaq: INTC - news - people ), this is a market that it barely seemed to even notice in the past. But with cellphone sales now surpassing the 1 billion mark and computing being done even by non-traditional computers, the company clearly sees the need for expanding beyond its traditional boundaries. Forbes caught up with Pat Gelsinger, senior vice president and general manager of Intel's Enterprise Group, to talk about the new strategy. Forbes: Intel's direction for decades was faster processing and more power. What's changed?Pat Gelsinger: If I'm doing a Google map, I don't want the entire planet represented on an iPhone. That's an enormous database, and I need just one little piece of that. That's the quintessential cloud. There is a large aggregation of data or services on the back end, a small amount of data and bandwidth that you need to provide to it. Those applications are ideal for the iPhones of the future. If you look at the three basic elements of a computing resource, it's processing, storage and communications. But communications is the weakest of the three. Moore's Law applies directly to processing. Storage is growing faster than Moore's Law. Communications is growing significantly slower, so applications that demand high bandwidth never effectively use a cloud model. Those are the three legs of the stool that you're always working with inside of computers, right? Yes, and applications that rely on large data sets and small bandwidth are well suited to cloud computing. Those that require high bandwidth and high visualization or user interface are very bad for those environments. The other limiters for cloud are associated with things like security, privacy and identity. Having said that, cloud applications will be a key part of the consumer and enterprise experience. I suspect that enterprise data centers will look like virtualized data centers in the future. They end up being the intranet cloud because of the scalability of resources, load balancing and energy efficiency. Threading of software delineates what goes where on a core. How does that change with more cores? Comment On This StoryOne of the cool features of Nehalem (Intel's code name for its next-generation general-purpose processor) is turbo mode. If you only have one thread to run, it gives all the power of the die to the core that's running that thread. If you have four threads to run, it spreads the power across all four cores. Dynamically this intelligent architecture adjusts from single thread to multithread and turns on and off portions of the die to accommodate that. So basically this is an on-chip traffic cop? Yes, you can think of it that way. It's like throwing a breaker switch to that portion of the die. This is one of the product design trade-offs we've introduced into Nehalem. Our basic tenet is that with every new generation, the core gets faster on single-threaded applications. And we scale more dramatically with core count. But that performance increase on a single core doesn't grow as fast as in previous generations of single-core chips, right? Correct. There isn't a big knob of frequency anymore. Frequency is growing modestly. We're not leaping from 100 megahertz to 500 MHz to 1 gigahertz. Now we're going from 3 GHz to 3.3 GHz in far more incremental gains in frequency. My single-thread performance is at a more modest rate, and when I do turbo, I can do better. On top of that, my core count can scale. When you double the number of transistors, it's easy to double the number of cores. But we're not going to keep doubling the number of cores. Is it going to be a rational application of cores vs. just adding more and more cores, which was the prediction five years ago? Core counts in servers will continue to increase at a reasonably rapid pace. It won't double every generation. We've gone from two to four to eight. In the mainstream of clients, the core counts are far more modest. There will be two cores and some four cores, but that will be almost flat for the foreseeable future because the applications don't demand it. There isn't enough threading there to warrant a significant increase in core counts. The exception is that we are looking at Larrabee (Intel's upcoming high-performance server chip), which uses a visual computing co-processor to attack high-throughput workloads. So something like ray-tracing graphics would work fine for that, right? Absolutely. And it turns out that graphics rendering is extremely parallel. If you carve up your screen into blocks, and one core owns the upper right block, the next core owns the block next to that, and so on, and then you do some cleanup at the edges, it's essentially an infinitely parallel task to render. Why is that? With ray tracing you have a thread for every ray you're shooting through an object or scene. Many of the physics algorithms are extremely parallel, as well. As we look at Terascale applications, we find highly scalable algorithms in many areas of computing. That might be in financial services, oil and gas exploration, image modeling, and human interface and recognition. What are Terascale applications? It's this categorization of applications that need a teraflop of computing, a terabyte of memory and terabit of communication of bandwidth. As we get to this teraflop level of performance--in some applications it may be half of that or 5 teraflops, which is the biggest supercomputer five years ago--you can solve a lot of problems you wouldn't even think about before. There are gaming applications, but a real world example is volume rendering. It's a technique used by all MRI or CAT scan analysis. There is so much noise that you need to volume-render to pull out an image. This ends up being an extremely parallelizable application. The Mayo Clinic has done a paper with us. They can do things in real-time that were previously off-line tasks. A CAT scan becomes a real-time event. So Intel is going after all the markets it can? It's anything that computes. If there is a computer anywhere, that's an interesting market for us. Clearly we are targeting the price points of these embedded markets, as well, and we're bringing a huge software stack with us. Software development for embedded chips is going up three to four times. We have had the solution for years. We just didn't know how to package it. 2月17日 威盛欲当寨王 笔记本行业遭遇生死之困威盛欲当寨王 笔记本行业遭遇生死之困http://www.sina.com.cn 2008年11月03日 01:14 IT168.com 作者：盘古之心 山寨的背后，蕴含的不仅仅是资金链条的传导，同时也意味着正规军的苦恼，为什么同样是山寨模式，手机能够逼宫正规军，而且曾经在全国各地全面开花。很多笔记本厂商的脑海里面，也正在憧憬未来大把赚钱的美梦。
就在10月28日，威盛在深圳召开“开放式超移动产业策略联盟发布会” （Globle Mobility Bazaar)，与微软合作，并联合15家PC业上中下游厂商，包括联电旗下的联阳半导体、Sandisk、AMI等在深圳宣布成立“开放式移动平台产业战略联盟”，抢占国内便携笔记本市场。 为什么威盛会把自己放在如此突出的位置？做为世界上仅有几家有能力研发并制造中央处理器的企业，原先低调的威盛电子在近期的动作频频。面对 CPU领域的传统巨头，Intel以及AMD，威盛从来没有一款产品可以超越Intel的同级别产品，但Nano的诞生这种局面可能会被打破。 笔记本山寨化冲动的背景 Intel就曾经被自己的Atom处理器搞的麻烦异常，就是因为无法处理好Atom的定位，以及和自家的其它处理器的关系。自COMPUTEX 上发布Atom以来，Intel这种针对低功耗市场的产品就一直受到各大合作伙伴的支持。来自华硕、Acer、戴尔等多家OEM大厂均要求提高Atom的出货量，Intel为了让Atom停留在消费类市场，避免渗透到商业市场以影响主流的迅驰平台的销售。全球经济总体前景并不被看好，不过低价电脑销售却异军突起，Atom处理器持续缺货，供给量无法满足伙伴的需求，导致许多OEM厂商转向威盛采购C7-M或Nano处理器。而Intel至今也没有积极地调整以增大Atom的产能，预计Atom占第三季度OEM处理器总出货量的3%，第四季度才会提升到5%，明年上半年也会维持在5%左右。
英特尔Atom处理器展示
威盛Nano处理器展示 正是因为策略性缺货这样的事件，所以市场更加需要类似威盛这样的企业积极介入。同时，因为市场中对于netbook的需求持续走高，使得威盛的解决方案成为了Intel Atom缺席后的最好补充。其实无论对于Intel还是AMD来说，其实对于进入netbook市场，是心存芥蒂的。这个市场的空间到底有多大？后续的发展空间以及增长速度能有多少？在目前这样全球性的经济不景气的环境里，消费电子的未来充满了不确定性。而做为消费电子巨头的索尼，也已经因为日元升值以及需求低迷、持续亏损等原因，持续下调09年的营运预期。就连一向对消费电子领域充满自信的索尼都看淡后期的营运状况，那么谁能够漠视如今这样低迷的环境那？ 抱团取暖 联盟背后的生存危机 拯救别人不是为了成为救世主，而是为了拯救自己。也许就是因为这个原因，所以当威盛电子牵头组成这样的联盟，那么让我们先看下，这个联盟的参与者以及分工吧，或许能够令我们可以更加清晰地看透其中的玄机。“开放式移动平台产业战略联盟”——GMB由威盛主导成立，微软（MicroSoft）、联阳（ITE)、AMI、新帝（SanDisk）等多家业者参加；由威盛提供处理器、芯片组等关键晶片，由联盟伙伴提供软、硬件配置，再由国内某家一线 OEM厂将负责代工制造。
有业界人士表示，这样的联盟，从实质而言就是正规军打不起消耗极大的阵地战了，转而走“小、快、灵”的山寨路线，而联盟的诞生，其实就是Intel CBB计划的Copy，只是在细节上做了调整，而实际的运作方式从目前的产业环境分析看，应该是大体一致的。
在国内的OEM厂商持续低迷的背景下，向渠道大批压货以及低价促销的方式都无法拯救自身，那么就只能把命运寄托于一种希望。这种希望就是山寨化冲动的起源。生存带来的危机，会不可遏抑的传播开来，影响每一个在市场中打拼的厂商，而这一系列的动作将会是致命的。以至于这些厂商不得不冒山寨的恶名，去为了自己的生存而尽最后的一丝努力。 未来netbook路在何方 由于威盛的Nano在对决Atom上面，在性能上面很有优势，而且保持了一贯的低功耗传统优势，如果在现在大量供货的，很有可能会一举拿下 netbook的半壁江山。但是事情不会这么顺利，Intel也意识到了Atom，将会是刺激消费市场的利器，在考虑利弊得失之后，Intel勇敢地公布了后续的Atom双核版本，并且承诺会在适当的时候推出，通过一些国外媒体的评测，Atom双核的性能得到了不小的提升，而根据威盛方面的公开信息，双核版本的Nano很可能需要在09年Q3之后才会推向市场。
由于各方面的原因，威盛电子面临着好坏参半的局面，致力于依靠“开放式移动平台产业战略联盟”来实现自身的蜕变，从而实现过去的辉煌，这一直是威盛想要的目标。而Intel来说，Atom只不过是它向新兴产品市场投的一块石子，正是因为华硕的Eee PC，才能得以激活netbook市场。当然很多分析人士以及众多媒体，也纷纷表示，netbook绝对不是拯救笔记本市场的救世主，但是从目前的糟糕状态看，谁不做这块市场，谁就得承担预期的风险，这也正是戴尔、惠普在netbook市场不断投入的理由。
众多上网本产品展示 而对于威盛而言，如何巧妙的运用时间差，来爆发出一场全面的“Netbook人民战争”从下到上的提出完善的低成本解决方案的话，那么未来可期，成败可图。就算是做到最后，发现已经无利可图，也会让Intel相当难受，毕竟群众的眼睛是雪亮的，能够分辨清谁在张着血淋淋的大口吞噬自己的血汗钱。而谁能够在较低的成本控制下，为群众提供真正方便好用的netbook。所以还是让我们拭目以待吧，等到尘埃落定的那天，一切都会变得不那么重要。 8月11日 刚刚review的一篇文章被导师催着review一篇文章，文章写得so so，竟然还是某业内知名会议的best paper candidator，现在这行的学术圈越来越funny了。随手把我的review贴在这里。“There are three kinds of lies: lies, damned lies, and statistics.” The research topic in this paper is quite interesting. People have worked on within die and die-to-die variations for years. However, there are very limited data disclosed to academy and most of research (such as SSTA) is based on artificial assumptions of process variations. Precise and accurate statistical models and data would have significant contribution the progress of all related research. First of all, the author claimed they proposed a "xxxxxx" system. It seems the system is based on the frequency testing of RO. Honestly, I don't see any obvious difference between "xxxxxx" and traditional RO testing. In the section III, the title is "xxxxxx", but all of the details are telling RO testing and I can not see any unique tech from traditional ones. The authors need to clear point out what are THEIR contributions. Moreover, the authors claim "xxxxxx" as a system of extracting process variations. In fact, RO is only sensitive to performance related process variations. There are so many other properties of devices which are very difficult to capture the variations by RO. The authors seriously overestimated their contributions. In the next section, the authors introduce Kolmogorov-Smirnov test and existing statistical models (Matern model) to analysis the experimental data. Thus, the value of this paper is strongly dependent on whether the authors figure out to apply a better and efficient model for the experiment data. Unfortunately, this paper chose RO data of FPGA testing results. Though FPGA has the advantages on price and testing cost, FPGAs are very difficult be with cutting edge process tech and their variations are relatively much smaller. For example, in Fig.5 (c), the min-max difference is only 2ns, while the mean delay is 80ns. The sigma might be less than 2/6/80 = 0.5%, (assume min-max is 6 sigma). The tested delays are very stable and variations are very trivial. Similar conclusions can also been drawn from other figures in the paper. From above, we can see no matter the adopted statistical model and testing tech suitable to capture the process variations, the experimental data are not suitable for this research topic and there are very limited chance to value the contribution of this research. I strongly suggest the author to get some data of Process Control Monitoring or similar techs to test more complement parameters of single device besides RO. Less number of devices in each testcase might capture the variations more remarkable. Moreover, in the current statistical model adopted in this paper, there is no difference between x direction and y direction. One of the natural instincts of modern poly gates placement is that they more like to be in one direction. As gate width is much larger than gate length, the process variation and spatial correlation in x and y directions might be significant different. This can also be observed from the figures in this paper while omitted in the models. There is necessity to improve the statistical model. 10月10日 Gartner predicts soft landing for chip market in 2007Gartner predicts soft landing for chip market in 2007 Peter Clarke LONDON — Market research company Gartner Inc. has predicted a soft landing for the global semiconductor market in 2007, saying it expects annual growth to stay at a single-digit percentage, after achieving 8 or 9 percent in 2006. While the first half of 2007 will be slower than the seasonal norm, the market will turn and recover in the second half of 2007 and build thereafter to propel the market to between 10 percent and 20 percent growth in 2008, Gartner said. Gartner expects third quarter 2006 global semiconductor sales to be $62 billion, it said in a weekly note sent out Monday (Oct. 9). If followed by a relatively flat $65 billion in Q4 would take annual sales toward $246 billion, and an annual growth rate of 9 percent, it continued. Elsewhere in the same note Richard Gordon, Gartner's managing research vice president for semiconductors, discussed a statistical analysis of World Semiconductor Trade Statistics data which showed that 2006 annual growth would be somewhere between 3 percent and 14 percent but with a most likely outcome of 8 percent. "A double-digit growth rate for the year is increasingly unlikely," Gordon said in the note. However, 2007 is even harder to call Gartner said because of a lack of large movements at present. "There is no obvious turning point in the short-term outlook to suggest either a strong positive or negative growth trend in the first half of 2007," the report said. That lack of a market turning point has led Gartner to predict a soft landing, subject to such caveats as "using normal seasonal growth patterns" and "assuming market conditions remain controlled." "We expect the three-month and 12-month growth curves to trend slightly lower through the first half of 2007 after a mini-peak in the fourth quarter of 2006 before bottoming out and recovering during the second half of 2007 and into 2008," the newsletter said. As a result it predicts a second year of "single-digit" growth.
9月15日 我现在非常艰难——英特尔员工惶惶不可终日（转载）我现在非常艰难——英特尔员工惶惶不可终日 "现在我情况非常艰难，你要是不能理解，我们就分手！"已经是美国西部时间晚上10点多，王涛放下电话，又一次有了内外交困的感觉----这种感觉，他在七年前刚到美国时有过，那一年，他和一同从北京来纽约的妻子离了婚。 现在，王涛和身在上海的女朋友又到了濒临分手的边缘，而起源正是今年7月开始的公司全球裁员计划。现在，他仍在美国硅谷Intel总部工作，但职业生涯的压力，第一次如此真实的出现。 这同样是Intel的压力----上一 次大规模裁员，已是十年前的事情。三个月前，Intel发布了有史以来"最令人失望"的一份财报----2006年第一季度净利润同比下滑了38%，今年 以来的股价下跌了22%。今年7月，公司首席执行官欧德宁表示，必须削减掉冗员，为公司节减开支。随后9月5日，Intel宣布裁撤大约一万五千名雇员。 这是与公司规模相符的裁员链条----先是全球裁掉一千名经理，之后Intel印度裁掉一千人，紧接着9月初，Intel马来西亚也开始第二次雇员自愿解职（VSS）计划，最终可能裁员一千到两千人；而以色列、新加坡等也都进入了裁员范围。 2004年7月，王涛进入Intel做芯片研发。他喜欢以工程师文化为主导的企业文化——只要做好自己手头的技术活，其它轻松而简单。他的经理Brown每天早上11：00到办公室，对下属非常宽容。周末是固定的休息时间，王涛和朋友相约去打篮球，跑步，去郊外爬山，这样的生活，稳定而惬意。 但这样的轻松王涛享用了不到两年。今年 6月，事情开始发生变化。一些陌生人出现在公司----他们开始在公司各部门进行考察和调研，并和员工进行询问和访谈，分析部门的业务和开发情况。"这是 专门请的一个咨询公司"，王涛说，公司内部隐约开始感觉到裁员的气息，"但那时候更多讲的是重组，把一些不赚钱的部门和业务卖掉"。 7月13日的早上，气息变成了实在的信号。王涛和其他员工一样，收到了一封名为"一个重要且艰难的决定：经理裁员"的邮件。而邮件的内容让他有些恐慌----"在公司全球范围内裁减一千个经理职位，这个决定影响到从公司高管到一线经理的各个层面"。 "第一个会是谁？"整整一天，办公室气 氛凝重。晚上，王涛第一次在电话里和女朋友发了脾气，虽然知道女朋友什么错也没有，但王涛也不知道自己哪里来的焦躁和不耐烦，同样是第一次不超过15分 钟，王涛就匆匆挂断了电话。"裁员只是经理层面，也许和我们普通员工没什么关系。"王涛这样安慰自己。 变化异常迅速。第二天一早，王涛走进 办公室，Brown已经在座位上了，而那是早上7:30。突然之间大家达成了共识，在办公室工作的时间更长了----以往6:30下班的时间自然被延续到 了9点以后，而王涛所属项目成员，也被Brown召集搬到了一个房间集中进行开发，"大家集中在一起便于讨论和沟通，有利于增加效率"，Brown的解释 让大家明白，今后要更加努力才会保住这份不错的工作。 至于以前被天经地义认为是休息的周末，也成了加班时间。女朋友在MSN上一个又一个的留言还有一封又一封的邮件，王涛都挤不出时间去细细回复。 8月5日，王涛所在部门宣布，在新的一批裁员名单中，在Intel长期实行"two boss"的管理制度（即一个部门有两个老板主管，或者两个部门并行，但同时两个老板主管）被暂停了，而被裁掉的就是不直接主管王涛的另一个经理。 "其实公司因为经理扩张太快，造成每个决定同期论证和达成共识的周期很长，所以每一项决定的效率很慢，这也是从经理开始入手裁员的原因。" 王涛说，这次所有裁员的部门和人员，都由咨询公司经过调查分析，按照严格的内部评估确定，这也是为什么这次裁员的部门还涉及一些赚钱的部门的原因。"通常一个经理带九至十个人才能形成一个部门，如果人数不够就合并，然后多余的就裁掉。" 王涛开始担忧，更意识到保住现在这份工 作的重要性。他给自己算了一笔帐----在Intel薪水每个月不到六千美金，养老保险和医疗保险每个月各交一百多美金，还要缴40%的税，另外还要供 车，每个月六百美金的房租，还有一部分要寄给国内的父母，当然还要为女朋友来美国读书存钱。 而压力仍在持续袭来。王涛第一次给女朋友的邮件里写到----"如此多的同事离开了公司，恶劣的工作环境让我无法平静，我感到巨大的压力。"那一天是8月19日，一个星期后，另一个项目组又被裁掉了。 对王涛来说，"最差的结果是被裁掉，那 我就重新去找工作，或者回国"，他很平静，"虽然比不上其它一些地区的补偿，毕竟总部这边还是给了（N＋3）X的补偿"，王涛讪讪的说，"不过，我知道中 国区被裁撤的员工还可以申请转到Intel其它的部门，总部这边不行，被裁掉就一次性走人了"。 对被裁员工去竞争对手AMD的传言，王涛表示自己对AMD兴趣不大。"Intel很多部门的业务现在AMD还没有做呢。" 9月13日 Paths to better timing analysisMy advisor and my colleague's work is reported by EETimes. Here it is.
Paths to better timing analysis Richard Goering EE Times (04/17/2006 10:00 AM EDT) A number of ISPD 2006 papers delved into timing analysis. Researchers from STMicroelectronics and the University of Montpellier (France) presented a technique that accounts for supply voltage and temperature variation. Arguing that a statistical approach cannot accurately capture deterministic voltage and temperature variations, the paper proposed using nonlinear derating coefficients for capture. The method first uses Synopsys Inc.'s PrimeTime analyzer to run a basic timing analysis for a given corner. Next, all timings are recomputed for the temperature and supply voltages provided. Propagation delay values are computed using traditional timing-library files, and then the final delay values, including variations, are obtained. The University of Maryland addressed a vexing issue for designers of nanometer ICs: How can you tell whether one design solution is better than another in the midst of process variability? Typically, a better solution is superior with respect to timing or cost. But process variations randomize the timing and cost, noted Vishal Khandelwal, a PhD candidate at the university. Get out the shears What's needed, he said, is a way to "prune" probability so as to discover the solutions that are probabilistically superior. The paper presented a "conditional" Monte Carlo technique using analytical bounds and a joint probability-density function that's computed mathematically. Two papers looked at variation with respect to clock networks. The University of Arizona proposed a statistical-centering-based algorithm that improves skew tolerance to interconnect variations. It also described a variation-aware abstract topology-generation algorithm. The techniques claim to reduce skew violations by 12 to 37 percent. The University of Texas at Austin proposed a unified algorithm for synthesizing a variation-tolerant, balanced, buffered clock tree with cross-links. Unlike previous link-based approaches, said UT professor David Pan, this work doesn't require expensive "tunable" buffers. -- Richard Goering 9月9日 Variability Fingered as Next Design PotholeRichard Goering EE Times (07/31/2006 9:00 AM EDT) San Francisco -- The effects of process variations loomed large at last week's Design Automation Conference here, as leading-edge chip designers spelled out the challenges they face at 65 nanometers and beyond. But many offered differing views and approaches for dealing with the problem. One quandary facing chip makers is whether to try to model everything using design-for-manufacturability (DFM) tools, or to employ restricted design rules (RDRs) that will result in more regular fabrics. Discussions last week showed that designers are hoping for a balanced approach that involves some restrictions, but leaves enough area and performance on the table so there's still some point in going to lower process nodes. Another issue that's unresolved is whether and when to use statistical timing analysis. Some designers are clearly skeptical, believing that it's effective for random variations only. In any case, there seems to be support for separating out systematic variations and modeling those before going to a statistical approach. But one thing is clear: users who have delved into 65 nm are feeling the pain. "My biggest concern at the 65-, 45- and 32-nm process nodes is variability," said Ho-Kyu Kang, vice president at Samsung Electronics. "Critical design rules have been scaled by 30 percent every other year, but variability has not scaled by the same rule. So variability becomes bigger and bigger as design rules scale." STMicroelectronics foresees a "discontinuity" with respect to the design tool solutions needed at 45 nm and beyond, said Philippe Magarshack, vice president of central CAD at STMicroelectronics. "We're dealing with restricted design rules on the one hand, and on the other looking for any way we can to predict system variability and account for it in design, rather than with design margins." Clive Bittlestone, fellow and physical verification manager at Texas Instruments Inc., noted that simple corner analysis with margins is becoming a struggle. "That keeps me awake at night," he said. "It's a key shift." Most design-for-manufacturing effects are served by available tools, but "true" variability analysis and ptimization is still needed, he said. What's most bothersome? Bittlestone showed a list of design concerns at various process nodes. His top concerns at 65 nm are gate shape, design rule checking, models, statistical timing analysis and placement and routing. Critical-area analysis, stress and extraction ranked lower. Aggressive users often feel shortchanged by commercial EDA vendors. But Magarshack said users can't expect tools too soon. "Until we do designs at these nodes, we can't prioritize the issues and ask for solutions," he said. "There are no tools for 45 nm for us to use--that's obvious. So it's crucial to have good working relationships with the right partners." In one panel discussion, Wally Rhines, Mentor Graphics Corp. chairman and CEO, asked user representatives why EDA revenues are flat while semiconductor revenues are up. "We have to provide better value every year," replied Gadi Singer, vice president and general manager of Intel Corp.'s low-power IA and technologies group. "The EDA industry has solved enough problems to stay in one place. If you can cut the cost of a project from $50 million to $30 million, we won't have any problem investing in EDA." There is widespread agreement that design rules will be at least somewhat restricted at 45 nm and below. Keynote speaker Hans Stork, senior vice president and CTO at Texas Instruments, noted in an EE Times video interview that DFM will not be able to model every detail. "The space is too complex and there are too many options," he said. "We will have to put some rules in place to structure the design." In a panel discussion on variability, moderator Bill Joyner, director of computer-aided design and test at Semiconductor Research Corp., presented eight hypothetical EDA companies and asked panelists where they'd invest. It's perhaps significant that one of the top choices was a company that offers variation-resistant regular fabrics. Another consistent choice was a startup offering lithography and process variation modeling. There was far less interest in extraction, placement, routing and yield optimization. "We shouldn't forget robust design rules and layout policies to minimize variation in the first place," said Vijay Pitchumani, project engineer at Intel. There were warnings, however. "We've had RDRs for a long time, and they just get more restrictive," said Dennis Buss, vice president for silicon technology development at Texas Instruments. "But you have to be careful. How can you put poly in the same direction or pitch without extensive sacrifices in area?" Tighter design rules, he noted, must still allow designers to achieve smaller areas as they go down in process nodes. "Regularity is a good thing, but RDRs alone are sort of a reverse scaling approach," said Dennis Sylvester, associate professor of electrical engineering and computer science at the University of Michigan. There are alternatives, he said. One of them derives from the observation that isolated and dense lines show opposite behavior under varying defocus conditions. Mixing isolated and dense cells can compensate for variation with seven times less area penalty than single-pitch RDRs, Sylvester said. Random, systematic variations Designers have long noticed that some variations are random and statistical, while others are systematic and can be modeled. Intel's Pitchumani said it's best to model deterministic variations first. This would include device variations such as lithography effects, most interconnect variations including lithography and chemical-metal polishing (CMP) effects and most voltage and temperature variations. The variability problem, said Riko Radojcic, design-to-silicon initiative director at Qualcomm CDMA Technologies, is really an "accounting" problem. "Process corners are too wide," he said. "We put all sorts of variation into one set of corners." So what to do? First, he said, "peel out" the systematic effects. If an effect can be modeled, Radojcic said, do so, and then design around it and take it out of the corners. This would include lithography, CMP, orientation, density and on-chip variation. Second, Radojcic said, don't use corners based on immature processes. "Beat up on the foundries for predictive models of how the corners will be a year from now," he said. "They'll be less pessimistic." Once this is done, designers can focus on truly random, statistical variations, he said. Radojcic said he expects the design flow to remain pretty much the same, with some added capabilities such as a shape simulator for lithography effects. "If all else fails and I need to deal with statistical variability, I'll go to statistical timing analysis," he said. "Statistical timing is a good idea so long as you don't assume that variations are statistical," said TI's Buss. About the only thing that's truly statistical, he said, are random dopant fluctuations. With anything else, statistical timing may give the wrong answer, Buss said. But ST's Magarshack is more positive about statistical timing. "In real life, I believe we cannot accurately predict temperature and voltage variations," he said. "We may have to take a statistical approach to compensate for these unknowns." So far, however, there's little designer buy-in for statistical timing, observed Sylvester of the University of Michigan. There may be an alternative approach to statistical optimization, he said, that relies on deterministic formulations and "intelligent variation space sampling." Cost, density, power Variation isn't the only concern of the power users now moving to 65 and 45 nm. For TI's Buss, the biggest concern is the high cost of custom designs. With design costs around $50 million, he said, "low-volume ASICs will become a thing of the past." The cost is impacted dramatically, he said, by power-management needs, parametric variation and system-on-chip integration, including analog components. Intel's Singer outlined four major nanometer design challenges. One is increasing density, leading to a huge logic capacity; another is increasing complexity, with technologies such as multiple power domains. A third challenge, the convergence of computing and communications, creates low-power demands. The fourth challenge is time-to-market. With more analog circuitry being integrated on-chip, analog/mixed-signal design was also a frequently cited concern. In that realm, said ST's Magarshack, "designer productivity has not improved significantly. . . . There's a lot of work for the EDA industry." 9月23日 清华梦的粉碎—写给清华大学的退学申请Quote 清华梦的粉碎—写给清华大学的退学申请 9月16日 华虹复兴聚焦王宁国 半导体业盘整大幕将启http://www.sina.com.cn 2005年09月17日 07:53 中国经营报
作者：文照谋
华虹集团再一次经历人事地震。近日，华虹正式公布，王宁国就任上海华虹(集团)有限公司CEO、上海华虹国际公司副董事长、CEO和总裁以及华虹半导体有限公司董事长。最近，王宁国已经代表华虹在美国活动。此前，王宁国是全球最大的半导体设备商——美国应用材料公司的全球副总裁和亚洲区总裁，他在那里工作了25年。
王宁国的跳槽，在半导体业界引起巨大反响，大都认为华虹这一次是“找对了人”，并把华虹重新崛起的希望寄托在王宁国身上。而记者获悉，在王宁国入主华虹的背后，是国内半导体业盘整大幕的即将开启。
华虹欲重夺老大之位
王宁国在半导体业界拥有极大影响力，对华虹来说，王宁国的加盟被赋予“重整”华虹的色彩。华虹是“国家909半导体工程”的主体，并在国内建成了第一条8英寸芯片生产线，之前一直是国内半导体制造业的龙头老大。但是，最近5年中，华虹的发展速度却明显落后于国内芯片制造产业的整体水平，尤其是随着中芯国际、和舰科技、宏力半导体以及台积电(上海)等多家企业的8英寸、12英寸芯片厂的陆续建成投产，华虹在芯片制造行业的影响力日渐下滑。
华虹一直在寻求突破，其中的两件事情颇受业界关注：一、寻求在海外上市；二、着手兴建12英寸芯片厂。但由于市场、资金等问题，几年来一直未能成行。
据知情人士透露，王宁国加盟之后的最大改变是华虹将以一家IDM公司为发展目标。王宁国最近也曾表示，内地的最大优势是拥有广大的电子消费市场，目前已有华为、海尔、联想等大型系统厂商，极有条件在发展晶圆代工、封测之外，培育出当地 IC设计厂商，建构起完整的半导体产业
供应链——这成为一种暗示。 另外，华虹也确实具备成为IDM公司的条件：在代工厂方面，它拥有华虹NEC、上海贝岭、上海先进半导体；在设计方面拥有北方华虹、南方华虹、华杰公司；它在封装测试领域也有投资。
台湾宝来证券分析师张立则向记者表示，如果华虹作为半导体代工企业在海外上市，很容易就会步中芯、华润上华股价持续低迷的后尘，但如果华虹能以IDM公司作为亮点，则可以摆脱它们的股价困局，因为IDM概念在中国目前仅此一家。
目前，华虹的主要盈利还是来自于代工业务，而且得到政府的支持。政府要求很多项目指定下单给华虹，而且价格比台积电等公司要高出15%。华虹在设计上的强项目前也主要是它的IC卡项目，其业绩主要是上海社保卡和交通一卡通。“整合上下游资源做IDM公司，如果能提高设计能力的话就会进展顺利，否则也就比较难。”张立评价说。
半导体产业酝酿盘整
王宁国加盟华虹，也成为是国内半导体产业新一轮盘整的开始。据一位业内人士透露，国家正在酝酿半导体产业的重组，其中首先很有可能就是华虹和宏力半导体在资本上、经营上进行整合，整合之后“可能会出现第四个大型的芯片制造集团(在台积电、台联电、中芯国际之外)。”
半导体业的整合态势预计不久之后将会逐渐明朗，首先被盘整的自然是其中的“国家队”。赛迪顾问半导体咨询事业部集成电路研究所所长李珂认为，2000年以来的5年间，国内半导体业快速发展，现在其实也是到了一个资源整合、行业盘整的时机。而且，资本层面的变更等也已经为整合提供了可能。
这次半导体业的整合既是政府的意愿，也是市场的需求。张立向记者表示，外资、台资半导体企业(如台积电、联电)进入内地的趋势已经非常明显，如果内地没有足够大规模的半导体企业，肯定是抗不过它们的。而且，华虹、宏力、华润等几家半导体公司还存在“内耗”现象，因为规模、技术等方面的限制，它们目前都只能集中在低端，而且低价抢单，高端领域根本无法染指(高端领域主要由台积电等控制，中芯在高端也还有一定的竞争力)，因此，整合对这些公司有好处。
另据了解，华虹的12英寸厂有可能将获得国有资本的投入，以支持它接手来自第二代身份证项目等政府订单。这也是政府欲做大产业的一个举措。
“在半导体业界，经常说只有第一，没有第二。”李珂表示，半导体制造业很强调规模，因此这种整合正在日益显示出它的必要性。而目前国内半导体业比较分散，多条大小生产线各自存在，要做大做强，整合似乎已经成为必须。
而显然，在这次整合浪潮中，华虹凭借其多方优势无疑处于中心位置。怎样去整合华虹自身，又怎样应对业界整合浪潮，其实才是王宁国入主华虹之后的主要考验。
背景资料
IDM模式，指从设计、生产到销售一条龙服务的芯片公司模式，即整合组件制造厂，如英特尔公司。FOUNDRY模式，指将晶圆制造环节委托给专业公司代加工的芯片公司模式，即代工厂，如台积电公司。这是目前两种芯片公司模式，各有优劣势。 8月31日 Since 1960, worldwide semiconductor revenuesSince 1960, worldwide semiconductor revenues have increased an average of 14.9% per year - see figure 1- Worldwide revenue trend. [1],[2],[3]. In figure 1, the dark green line is the actual revenue by year, the light green line is the overall revenue trend and the green triangles are the revenue forecast from our strategic partner IC Insights [2]. Note how the recent downturn has been so severe that IC Insights is forecasting overall revenue to finally exceed the year 2000 revenue in 2004, and then to fall back again in 2005. Figure 2 - Worldwide semiconductor revenue growth [1],[2],[3]. Note how the revenue growth rate depicted in figure 2 never actually grows an average amount, but rather exhibits large swings in growth rate.
[1] "World Semiconductor Trade Statistics," SIA, http:/www.semichips.org/pre_statistics.cfm. [2] "The McLean Report 2002 Edition: An In-Depth Analysis and Forecast of the Integrated Circuit Industry," IC Insights (2002). [3] IC Knowledge database. 8月25日 Cell: A Chip That's Going Public (zz)Cell: A Chip That's Going Public
UNDER WRAPS TILL NOW. According to Ted Maeurer, software manager in the STI Design Center -- a unit of the three-way joint venture that IBM, Toshiba, and Sony created around the chip -- there has always been curiosity about how the chip works. "The level of interest has frankly been difficult to respond to," he says. Charles King, an analyst with Pund-IT, a Hayward (Calif.) consultancy, says Sony, IBM, and Toshiba are meeting commitments made to software developers and interested hardware manufacturers earlier in the year -- and are doing it on time. "Great computer hardware is only a doorstop without great software," he says. The three companies have always intended for the Cell chip to be used in hardware other than the PlayStation 3, but until today they've kept technical details about how it works close to the vest. VIDEO-PROCESSING POTENTIAL. Still, some businesses have seen that the chip wasn't just fun and games. In June, Mercury Computer Systems (MRCY), a Chelmsford (Mass.)-based manufacturer of specialized computers used for medical imaging and military surveillance, says it plans to use the chip in an as-yet-unspecified application it is developing with IBM. The release of the information should encourage other companies to do likewise, King says. Indeed, the Cell has plenty of potential uses. Already, Sony and Toshiba are making an example of the chip's nongame potential. Sony plans to use it in a line of media servers, set to debut in 2007, that will be capable of transmitting several streams of digital video at once. Toshiba has said it expects to use it in a line of high-definition TV sets. "The sheer processing power of the Cell processor provides some very interesting capabilities for video processing," King says. Chris Crotty, an analyst with iSuppli, a San Jose (Calif.) market research firm, expects the chip could also be "a good fit" as set-top boxes evolve. Says STI's Maeurer: "This is really about exploring how far we can go with the Cell processor." Far beyond video games, it seems. 信产部集成电路发展报告 (zz)http://www.sina.com.cn 2005年08月22日 08:33 新浪科技 文/徐志斌 新浪科技讯 中国集成电路市场市场需求巨大，现状却不容乐观。 日前，信产部软件与集成电路促进中心发布了《2004年度中国集成电路企业发展状况及IP现状调研报告》。报告中指出，中国有着巨大的集成电路市场空间，数字电视、手机及计算机等的市场需求令国外商家都不敢忽视，但目前几乎所有的核心技术都掌握在外国公司手里。 从某种意义上说，中国还没有形成真正意义上的集成电路知识产权公司。纯粹依靠集成电路知识产权销售很难维持公司正常运转，因此国内的集成电路公司通常以知识产权销售＋传统的IC设计服务等为生。 “要想使中国的IP(知识产权)借助巨大的市场优势迅速成长起来，进而成为世界的IP中心，还有很多基础性的工作要做”，报告也提出了许多建言。首要两条就是建立有效的集成电路法律保护体系，和相关标准的建立。 中国集成电路设计意识落后 中国集成电路设计企业总数将近500家，除去以知识产权销售＋传统的IC设计服务这一模式外，国内集成电路研发企业也多采用另一模式，即从事设计服务。他们多拥有一定量的知识产权，不过，这更多是作为企业吸引设计服务的一种手段，依然缺乏核心的竞争力及市场手段。 报告在挑选调查了近百家集成电路企业样本，其中包括IC设计公司、Design house、科研院所、高校企业以及整机企业的IC设计部门，不仅包括了年产值超亿元的大型企业，也包括了产值在100万元以下的小型企业。 在经过详细的调查后，报告认为，与国外集成电路知识产权设计相比，国内企业还存在着巨大的差距，主要表现在三个方面。 首先在设计的意识上就已落后一步。国外同行企业一般瞄准的是两三年甚至是五年以后的中国市场需求，研究的是政府的产业政策，引领着未来的产业方向。而国内的绝大部分公司则跟着市场的产品价格走，什么产品价格高，需求大，就设计什么类型的集成电路知识产权设计。而当中国的公司设计出市场需要的产品时，往往这类价格已经降到很低。 其次是在商业模式上。知识产权是一种比较特殊的商品，从设计、销售到制造的各个环节都与芯片制造紧密相关，因此国外的公司通常都与芯片代工企业保持了良好的关系，形成了比较成熟的商业运作模式。而国内相关公司则处于起步阶段，很少有公司走完了从设计到销售再到制造，并将产权有效回收的全过程。 第三是在IP的设计技术上，国内很少有公司掌握了一整套设计技术。 集成电路发展不单是技术问题 在调查中，国内企业认为，知识产权授权费用太高成为国内集成电路知识产权使用的最主要障碍。同时，获得授权的海外企业知识产权的质量也没有一个合适的评估标准。 但报告中也指出，集成电路知识产权的保护不是单纯的技术或市场问题，还涉及到社会的诚信体系和法律体系的建设。 目前，中国集成电路正遭遇着一个发展机遇，巨大的市场需求成为发展的源动力，同时，集成电路制造业及设计自动化工具的发展也大大降低了入门门槛。而付费使用海外国家的设计授权，将发达国家用了几年甚至十几年积累起来的技术直接为我所用，也使中国集成电路跳过了漫长的积累阶段，站在较高的起点上发展。 报告由此建言，要将市场优势转化为技术领先，也需要做许多的基础工作。首先就是建立有效的集成电路法律保护体系，寻找知识产权技术保护手段。 现阶段与集成电路保护相关的法律及条例有《中华人民共和国专利法》、《中华人民共和国著作权法》、《计算机软件保护条例》和《集成电路布图设计保护条例》等。然而集成电路设计技术日新月异，设计方法和设计手段和十几年前甚至几年前相比已经有了本质的区别，而法律的制定显然没有跟上技术进步的步伐；其次法律还没有形成足够的威慑力量，让绝大多数的公司不敢以身试法。 其次是标准的建立及推广。值得注意的是，目前 第三是组织基础及关键领域的知识产权开发。最后，报告也指出，集成电路知识产权保护不好，不仅损害国外公司的利益，也会将刚刚起步的国内公司扼杀在摇篮中。
http://www.sina.com.cn 2005年08月18日 09:25 eNet硅谷动力 作者： 英宁 【eNet硅谷动力消息】日前由信息产业部、财政部联合主办的电子信息产业发展基金 “十五”成果汇报展示会上，信息产业部有关人士表示，“十五”期间,电子发展基金在软件产业的投入近10亿元，占全部基金的四成以上。“十一五”期间，软件和集成电路继续列为电子发展基金投入主要领域，并将追加基金投入。 我国自1986年设立电子发展基金，至今累计投入39亿元。“十一五”期间,除了在关键领域核心技术方面投入外，电子发展基金还将对国际化经营试点的本土企业产业化研发加大投入，培育基于本土的大型跨国公司。为了推动信息技术在国民经济和社会发展各领域应用广度和深度，“十一五”电子发展基金将将向关键领域核心技术，以及初涉国际化经营的本土大企业重点倾斜。关注于电子政务、 信息产业部强调，为了进一步发挥和扩大电子发展基金的引导带动作用，“十一五”期间，电子发展基金要对关键领域和重点企业给予优先支持，着力提升核心技术、核心行业和竞争实力，进一步加快电子信息产业发展由外延型向内涵型，由加工制造为主向集研发、生产、服务、应用为一体转变。在占“十五”电子发展总基金投入四成的基础上，“十一五”期间,我国电子发展基金将继续对软件和集成电路产业给予重点扶持，以提高研发和生产能力，实现我国电子信息产业的新突破。 统计显示，2000年我国软件产业总产值仅为593亿元，到2004年，这一数字达 2300亿元，年平均增速超过38%。目前国家规划布局的重点软件企业已达176家。在电子发展基金的支持和引导下，以LINUX为代表的基础软件及以此为平台开发的各类软件为打破国外垄断进行积极探索；各类嵌入式软件、数字电视集成电路、 8月22日 华南百家MP3工厂关闭 (zz)早在去年，针对当时MP3市场激烈的竞争局势，不少有远见的中小MP3厂家就已在思考退路。当时一家深圳MP3代工厂的负责人向记者分析，他们有三条路：一条是继续加大MP3业务的投入，在做代工的同时逐渐建立自有品牌，尽量避开国内竞争激烈的市场，转攻国外的非洲、东南亚、中亚等地；二是重点研发MP3的后续产品MP4，尽快抢占MP4市场；三是回到电子厂的传统业务——代工或者建立自有品牌的键盘、机箱、鼠标等外设业务。
一年后的今天，记者联系到这位负责人，得到的回答是“我们已经放弃了原有的MP3业务”，“人算不如天算，实际上目前国外的MP3市场，竞争同样激烈，不少厂商打出去后很快又退回来；而MP4，一年后市场依然不温不火，消费者接受程度相当有限，同时功能越来越强大的手机早已经在蚕食这块市场，MP4代工也难有乐观。”
对比阅读：
上个财季iPod销售收入与iTunes网络音乐商铺收入的总额占到了苹果全部收入的38%。 8月18日 中国电子百强利润下滑53% (zz)http://www.sina.com.cn 2005年08月18日 01:17 南方都市报 上半年利润率仅3%，电子百强企业1-5月利润同比下滑53%
中国电子工业告急 高速增长结束了，调整期已经到来！日前国家发展改革委员会和信息产业部发布的数据显示了我国电子工业的尴尬局面：生产和销售收入依然保持快速增长，但利润总额同比下降、应收账款增加较快，一句话，增量不增收甚至减收，已经困扰着我国的电子产业。
据信息产业部的数据，代表我国电子产业实力的电子百强企业，1-5月利润总额只有48亿元，同比去年下降53%，一些明星企业如TCL、京东方、华为等出现了较大金额的亏损，中国电子产业前景不容乐观。
上半年增量不增收
发改委公布的上半年我国电子工业经济运行情况表明，在经历了2003、2004年生产和效益的高速增长后，今年以来电子工业进入产业结构调整期，生产和销售收入保持快速增长态势，利润总额同比下降、应收账款增加较快。
上半年，全国累计完成工业总产值(现价)11496亿元，同比增长20%，统计的七个电子行业生产均实现了增长，其中，电子计算机制造业累计完成产值4340亿元，同比增长33.2%，规模和增速居行业首位，是拉动电子工业增长的主要因素。
另外，出口继续保持高速增长。上半年累计完成出口交货值7275亿元，同比增长31.3%；其中，电子计算机制造业完成出口交货值3395亿元，增长36.3%，是我国目前出口交货值最高的单项产品，也是拉动电子行业出口高速增长的重要因素。
但是，在销售收入快速增长的同时，利润总额却同比下降。上半年，全行业累计实现产品销售收入11141亿元，同比增长20.1%；实现利润总额336亿元，利润率只有3%，同比下降5.5%。
同样值得忧虑的是，应收账款增加较快，产成品库存较高。到6月末，全行业应收账款达到4202亿元，同比增长21.9%；产成品库存达到932亿元，同比增长8.7%。
3G决策滞后有负面影响
发改委在分析电子工业利润下降的原因时认为，一是通信设备制造业和电子器件制造业中部分产品面临升级换代期，换代新产品尚难形成较大的市场空间，致使销售收入明显下降。上半年，通信传输设备实现销售收入同比下降30.8%，亏损0.8亿元；通信交换设备销售收入下降7%，利润下降64.6%；电子真空器件销售收入下降15.5%，亏损2.7亿元。
二是国际集成电路市场疲软，产品价格下跌，我国集成电路全行业在销售较快增长的同时，利润明显下降。上半年，集成电路制造业实现销售收入488亿元，同比增长18.2%；利润7.6亿元，同比下降56.8%。
三是国内市场价格竞争激烈，企业以降价促销，增收不增效。上半年，家用视听设备制造业实现销售收入1357亿元，同比增长13.5%；利润25亿元，同比下降1.2%。
目前通信业正处在3G前夜，中国3G牌照迟迟不发，已经影响到了通信设备制造业和电子器件制造业的整体效益，而消费电子产业也处在
数字电视更新换代的等候期中，因此如果从电子工业的效益考虑，目前全行业效益下滑的严峻局势对3G和数字电视的尽快决策，会起到一定的推动作用。 电子百强利润下滑严重
代表我国电子工业大企业的电子百强的效益在上半年出现了严重下滑，根据信息产业部经济运行司提供的数据，1-5月份，电子百强企业累计完成营业收入3121亿元，同比增长6%(去年为增长28%)；实现利润总额48亿元，同比下降53% (去年为增长31%)，电子百强的整体利润率仅有1.5%左右，比全行业平均水平低了一半。一直以来，我国电子行业推行大企业战略，国家鼓励通过兼并、重组，成立一批具有规模经济优势的大企业参与国际竞争，但是目前大企业战略看来面临事实的质疑。
信产部认为，今年以来，国家继续加强和改善宏观调控，国际能源、原材料价格进一步上涨，电子信息产品市场需求放缓，市场竞争更加激烈，因此大部分百强企业出现增势减缓或下降态势。
据统计，1-5月，年营业收入超过100亿元的22家大企业中有8家营业收入出现负增长，其中京东方科技集团-18%、上海广电集团-22%、熊猫电子-21%、中兴通讯-31%、深圳康佳-20%。
1-5月份，百强企业实现利润总额48亿元，同比下降53%(上届百强2004年1 -5月为97亿元，增速为31%)。绝大部分企业利润都出现大幅度下降，百强前10家企业中有6家利润指标比去年同期下滑，3家亏损，其中京东方科技股份有限公司亏损5.15亿元，TCL集团亏损额达到10.8亿元，华为技术有限公司亏损2.8亿元。
华为称上半年盈利14亿
对于信产部的数据，记者联系TCL集团求证，TCL方面表示一切以发布的正式公告为准，拒绝透露亏损数额。从目前TCL发布的提示性业绩公告来看，TCL 6月份销售数据(未经审计)，彩电国内销量同比去年略有下滑，但是海外彩电销售增长了一倍多，而国内手机销量下滑很厉害，因此整体TCL集团6月份营收不会出现暴涨，上半年出现亏损应该是可以预期的。
但是华为方面提供的数据则称，上半年华为实现业务收入330亿元，利润14亿元，同比增长了20%，华为人士称，信产部数据也是属实的，前5个月华为确实亏损，但这是海外业务收入的账期导致的，6月份公司大量回款，因此整个上半年华为实现了巨额的盈利。
信产部的数据显示，排名11-20名的知名百强企业中，1-5月康佳集团利润同比下降44%，前50名中的彩虹集团利润同比下降37.2%，侨兴集团利润下降62%，夏新电子下降122%，广州金鹏下降121%。
出口增长是惟一亮点
在一片惨淡数字下，出口的快速增长成为上半年我国电子工业的惟一亮点，1-5月份，百强企业完成出口交货值899亿元，同比增长24%。其中TCL完成91.5亿元，同比增长37%；广东美的出口交货值69.9亿元，同比增长103%；华为完成61.9亿元，同比增长207%；长城计算机52.2亿元，同比增长57%。
信产部的分析认为，在国家“走出去”战略推动下，百强企业进一步加大国际市场开拓力度。比如海尔集团在约旦投资的工厂已正式投产，在拓宽中东市场进程中又向前迈出了一步。TCL集团中东分公司成立，业务横跨埃及、土耳其等中东各国，成为 TCL集团的“大中东区”业务的拓展中心。夏新电子借德国CeBit大展首次登陆欧洲市场，在不到一个月的时间内，已累计赢得千万元订单。与此同时，康佳中标家乐福法国总部的大额电视机采购项目，签下3万台出口订单。（本报记者 熊浩） 7月15日 Worldwide semiconductor market shareU.S.(45%) > Japan(20%) > Taiwan (12%) > South Korea(11%) > Europe(10%) > China
China and the rest of the world are each expected to achieve 2 percent market share in 2005, moving up to 4 percent and 3 percent, respectively in 2009. While IC consumption in China is forecast to be $84.4 billion in 2009, up from $31.0 billion in 2004, China's indigenous IC producers' chip sales in 2009 are forecast to be $10 billion, up from $2.3 billion in 2004.
Asia-Pacific companies' share of IC sales when excluding Japan was only 2 percent in 1982, according to IC Insights. The share grew to 9 percent in 1994 and more than doubled to 24 percent in 2004. With IC production by Asia-Pacific foundries expected to increase dramatically over the next few years, IC Insights forecast that the Asia-Pacific IC market share, including Taiwan, China, Korea and other regions, will reach 32 percent in 2009. |
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